A smaller die size isn't always better. In fact, it can significantly increase your cost per wafer if special care isn't give during the design process.
The chiplet would be laid out in a more sensible proportion, using the full 26mm width of the reticle as much as possible, and dividing the height by half, plus the overhead for interconnect. So the tool throughput will drop more like 10% (counting extra stepping movements and extra area), not 87%.
I agree, but this is entirely for demonstrative purposes of the concept. You know I only wrote this because of our argument + wanting to put number to the issue, and because I asked multiple architects about it, and they had no idea about the concept.
Most tool flows for anyone using these advanced tool flows will take care of the reticle layout optimization automatically. The architects would only need to be aware of the typical costs, not the worst case with bad layout.
It is also noticeable that we are seeing some fairly small chiplets, so people are moving towards the extreme of optimal yield and minimal reticle layout loss. This is likely driven by the new competence in high density, low latency interfaces between adjacent chiplets that reduce the cost of partitioning.
Googled some die sizes, and it seems like the most inefficient design is Navi 22, 18x18mm, can only fit one die per mask. That's like, 37% mask utilization.
The lithography tool then exposes through the photomask to print features on the wafer at 4x magnification. —> shouldn’t it read “at 4x reduction”? As the features on the mask are reduced to a smaller exposure field on the wafer
While the article raises a number of valid points, I don't think that this argument is supported:
> "The decision of chiplet vs monolithic becomes a lot more difficult now. Once you account for packaging costs, it is very likely the monolithic die is cheaper to fabricate."
If this were true, then why are chiplets becoming more and more popular?
It's not as if AMD, Intel and Nvidia didn't have people modelling this, too. The fact that we're nevertheless seeing more and more of chiplet designs would suggest that their models point to chiplets design still being cheaper.
The chiplet would be laid out in a more sensible proportion, using the full 26mm width of the reticle as much as possible, and dividing the height by half, plus the overhead for interconnect. So the tool throughput will drop more like 10% (counting extra stepping movements and extra area), not 87%.
I agree, but this is entirely for demonstrative purposes of the concept. You know I only wrote this because of our argument + wanting to put number to the issue, and because I asked multiple architects about it, and they had no idea about the concept.
Yes, it was fun to see it here.
Most tool flows for anyone using these advanced tool flows will take care of the reticle layout optimization automatically. The architects would only need to be aware of the typical costs, not the worst case with bad layout.
It is also noticeable that we are seeing some fairly small chiplets, so people are moving towards the extreme of optimal yield and minimal reticle layout loss. This is likely driven by the new competence in high density, low latency interfaces between adjacent chiplets that reduce the cost of partitioning.
"here is an old ASML slide the topic"
"here is an old ASML slide ON the topic"
"The evolution lithography spending versus deposition versus "
"The evolution OF lithography spending versus deposition versus "
"Let’s assume this foundry WHICH sells these wafers for ~$17,000 with a ~50% gr"
"Let’s assume this foundry sells these wafers for ~$17,000 with a ~50% gr"
Not sure about the last one. Great content as always
Oh man. It's clear I didn't proof this one enough. Thanks!
Googled some die sizes, and it seems like the most inefficient design is Navi 22, 18x18mm, can only fit one die per mask. That's like, 37% mask utilization.
Note that a mask can have multiple designs. Whose to say there isn't some other die on that mask? I mean I doubt it, but possible, but great catch.
The lithography tool then exposes through the photomask to print features on the wafer at 4x magnification. —> shouldn’t it read “at 4x reduction”? As the features on the mask are reduced to a smaller exposure field on the wafer
Yea it is. Thanks.
While the article raises a number of valid points, I don't think that this argument is supported:
> "The decision of chiplet vs monolithic becomes a lot more difficult now. Once you account for packaging costs, it is very likely the monolithic die is cheaper to fabricate."
If this were true, then why are chiplets becoming more and more popular?
It's not as if AMD, Intel and Nvidia didn't have people modelling this, too. The fact that we're nevertheless seeing more and more of chiplet designs would suggest that their models point to chiplets design still being cheaper.
Last paragraph...
"This example is a worst-case scenario chosen to demonstrate the point of reticle utilization rates."
"Most chiplet architectures are likely going to increase reticle utilization rates rather than decrease it."