In packaging, one size doesn't fit all
Great summary! I'd like to read other articles in that topic. :)
Yeah. But you talk about it somewhat in the article about Austria’s companies
A very competent review. Good to see that even the latecomer Co.s in Taiwan are at last wising up to Build Up Substrates of the CORELESS type, a technology developed in the early 2000s in AZ and put into HVM, just like most other Adv. Packaging technologies before and since. Dylan should look into the Cost vs Performance / Reliability Trade Off for the recent mutations by all the latecomers. The Performance of a Package ( e,g Eye Diagram ) depends on minimizing Parasitics. In that regard CORELESS BU Substrates have no significant disadvantage compared to FanOut WLP / PLPs. But the newcomers PEDDLED their Fan Out capability to IGNORANT fabless types on the technically dishonest ground of comparing the electrical performance of Fan Out packages to BU Substartes of the CORE type ! Cost of any Substrate / Fan Out depends on Panel / Wafer Size used as well as subsequent Processing like Wafer Bumping and Flip Chip Assembly. One of the Fan Out process with finest L/S described above has to use Bumping as a way to improve Pattern Recognition. And L/S for FO Packages is still limited by Die Shift, Molding Warpage etc. so they have to resort to TCB type Flip Chip Assy. So despite all sorts of intentional mis classification ( e,g. calling Flip Chip Packages Fan Out etc., to fool their ignorant Fabless customers ! ), over a decade after the introduction of Fan Out ( eWLB ). Flip Chip still has 90% of the Market. At the very finest end of L/S both technologies merge. So long as fundamental materials problems in Fan Out are not addressed ( the traditional developers of AP technologies in AZ are NOT interested, as EMIB on coarse & cheap Organic substrates takes care of their roadmap ) remains stuck at small wafer sizes ( 300 mm ) or large L/S ( > 5 um )
How do I access Part 1 to 3?
Finally the part 4 is here. Ha