20 Comments
Jul 25, 2022Liked by Dylan Patel

To keep costs of verification and respins low, the best ASICs are highly repetitious use of simple elements. Even if you take the time to customize the heck out of those elements, like Nvidia GPUs, overall the scale of the tools and the rules is local and then repeated to fill out the chip.

AMD is not that much faster than Intel. Sapphire Rapids had delays due to moving from Intel 7 to Intel 4. A good decision, but it is a reason for the maybe 7 respins. AMD have been talking up Genoa for years, so it was not super-quick. The interesting comparisons with Intel will be in the generation after SPR, when it looks like Intel will have the same kind of per-chiplet process specialization that AMD have pioneered, with similar advantages.

SPR is far more complex than an A100, in the sense that it has more specialized accelerators and other different kinds of functional units than Nvidia need to worry about. It is more interesting to compare Intel to Apple or to Qualcomm, other designers who have a ton of different functionality on their chips. These add to verification complexity.

The physical cost of making a mask is not so huge, if you separate it from design and verification cost. It takes a day or two of time on a dedicated ebeam machine to write the leading edge masks, plus some setup time to calculate how to modulate the ebeam machine to match the design. When a mask is respun for a correction, normally 99% of the mask does not change. This means that the respins should be a minor fraction of the costs associated with the mask set. Most of the cost is in the first mask set, that requires full validation, full rules check, and comprehensive corrections for predicted manufacturability. Those keep a large team of engineers and their most expensive tools busy for months. The iterations are a smaller loss of time plus payments for running the extra pilot set of wafers to check the design.

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Sapphire Rapids is still 10nm/Intel 7. Even the fastest multibeam mask writer takes ~12 hours to write a single mask. A node like N5 uses in the teens of EUV masks + another 50 or so DUV ones.

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The names and processes both evolved. SPR is for all practical purposes on a different process than it started, more a foundry issue than a CPU issue. It will have needed reverification and new layout, even if it kept the floor plan fairly constant.

There are multiple mask writer machines for hire. Most respins will affect only a few masks, they long ago learned tricks to allow local some slack for local patching without disturbing the higher metals, unless you are quite unlucky with the kind of fix needed.

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Jul 25, 2022Liked by Dylan Patel

As you state, metal only spins are cheaper and quicker (usually because many wafers are held at contact) and the upper metals are at reduced resolution. However, the term respin (in all the teams I've worked with) has always meant base layers which are multiple masks plus most of the lower level metals. At these advanced nodes, the lower level metals have very strict rules and require fine resolution. In summary, for these advanced nodes, mask cost of a respin is asymptotically closer to new full mask set.

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"usually because many wafers are held at contact"

Are you referring to how wafers are often only processed up to the Contact later, and only a few are pushed forward until they are qualified and bring up is complete?

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Sorry for delayed reply - didn't have notifications enabled. Yes, typically wafers of new designs are held at contact until some (company/team dependent) bringup threshold has been attained. If a metal only issue is found, then the time intensive base layers have already been processed and handfuls of weeks may be "saved" as the metal only processing has a shorter cycle time. Of course the cycle times for different layers vary by node/foundry.

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Thank you, and is this universal or do only a handful of companies and teams do this?

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It's an evolution of Intel 10nm, but it's still by and large a similar process. Same geometries except CPP relaxed.

Intel 4 is the actual shrink and big changes, but Intel 4/3 don't come to server until Granite which is 2024..

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AMD was not talking up Genoa for as long as Intel talked up even Ice Lake, which in theory was done in a by then mature node, never mind Sapphire Rapids which was supposed to initially come out in 2018 if I remember correctly. Also, Sapphire Rapids is being done on a node that has been used for ADL for a while, it's not like it's something in the bleeding edge. AMD has issues and delays, but they are definitely not as bad as Intel has been having for a while.

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Jul 25, 2022Liked by Dylan Patel

looks like even for 7nm, total fixed costs converge around 10k wafer run, that is, 10k is probably the floor for any independent ASICs. There's also an opinion that given current market situation, its versatility and programmability, Nvidia's A100 is still the cheapest option for data center AI service, which is bad news for start-ups. An interesting architecture is still long way from mass adoption. By the way, why is Intel's cost for verification and validation per node much higher and takes longer than AMD and Nvidia? Is it because Intel did it in-house and competitors outsourced?

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Jul 24, 2022Liked by Dylan Patel

Very helpful to understand where this is headed.

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SWOT Yokogawa minimal fab

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I don't follow... What do you mean?

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Strength Weakness Opportunity Threat analysis ... I like Yokogawa minimal fab. Your take, please?

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Right now is the exact right time to study substrate producer AXTI. The market for specialized chips will be increasing and this will cause demand for AXTI to really increase revenue and profit. The company has increased production capacity and is in great shape. Study both its production capacity and what the recent news represents in future valuation. Plenty of info on the website do the homework.

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Low liquidity small cap, website landing page is to investor relations not product, their SSL is expired.

Too many red flags in 30 seconds to be worth truly investigating.

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Guess who can have economy of scale, efficient supply chain and a huge number of STEMs who's secondary language is mathematics...

Hint 1: It's not the US.

Hint 2: It's not Taiwan

Hint 3: It's not South Korea

Please share your opinion :)

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These economics apply to everyone. The stark difference being that Chinese govt money and private capital incentivized by certain policies is more willing to have a lower success rate hence more startups, more will fail, but more successes too.

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"Semiconductors are an industry of economies of scale, and this is only becoming more apparent with each new technology generation."

China has scale, and more money than God.

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